The present invention relates to a computer system in which a single memory apparatus is shared between a central processor unit and an external processor units for common use thereof, the external processor unit being adapted to read out predetermined bytes of data from the memory apparatus periodically within a predetermined period of time.
In such a computer system, a CRT (cathode ray tube) display apparatus may be employed as the external data processor unit. In such a case, a pattern is repeatedly displayed with a frame frequency of 50 cycles/sec. in consideration of phosphor decay time and flickers of the pattern of frame. Under these conditions, for a CRT display apparatus capable of displaying 24 lines, each line consisting of 80 characters, i.e. 1920 characters in total, it is required that 80 bytes of data for one line display (one byte of data corresponds to one character) have to be read out from the memory apparatus within a period of about 800.mu. sec. Usually, a CRT display apparatus includes a buffer memory of a capacity to store data for one line. The data read out from the memory apparatus are stored temporarily in this buffer memory and displayed as one character line on the CRT after having been converted into a cooresponding character pattern. When a time span of 800.mu. sec. corresponding to a time duration for one line display has elapsed after the storage of the character data in the buffer memory, it then becomes necessary to write in the buffer memory new data of 80 bytes in the time span of 80.mu. sec. (corresponding to a duration of a single scanning line) for preparation of display of a succeeding line. In this connection, it is noted that the memory apparatus may not have accesses simultaneously from both the central processor unit and the CRT display apparatus for the read-out or write-in of data. Consequently, in the case of a known computer system in which the central processor unit is allotted with preference or priority for use of the memory apparatus, there may arise a possibility that a required number of data can not be read out by the CRT display apparatus, eventually resulting in occurrence of flickers and generation of somber patterns. In another type of the known computer system, use of the memory apparatus by the central processor unit has to be interrupted with undesirable frequency.
An attempt to eliminate the drawbacks described above is disclosed in Japanese Laying-Open of Patent Application No. 50-110233 (1975) "Control System for Display Apparatus." This patent application relates to a control system for use in the case where a display apparatus is connected to a data processing apparatus of a stored program type. In particular, there is a discription about an embodiment shown in FIG. 3, right lower column, lines 9 to 17, page 2 of the specification of the above-mentioned Japanese Patent Application. According to the description, an arrangement is made such that data transfers between a memory apparatus 5 and a program processor 10, on one hand, and between the memory 5 and a DMA (Direct Memory Access) control 11, on the other hand, are performed alternatively for every memory cycle. With such an arrangement, the program processing can be executed independently from the DMA control, whereby the data transfer to the DMA control can be carried out without fail for every memory cycle. Thus, even when the program processor enters into processing of a length command, there will not arise such a case in which the data transfer to the DMA control 11 is interrupted for a long duration. In this way, DMA data transfer efficiency is enhanced to prevent the produced pattern image from becoming gloomy.
However, the just above-mentioned system has a serious disadvantage that the program processor unit is permitted to make use of the memory apparatus only during half of a memory cycle, which results in a reduced processing efficiency of the processor.